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REV. B
DAC8043A
–3–
ABSOLUTE MAXIMUM RATINGS
*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±18 V
RFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±18 V
Logic Inputs to GND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VIOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/
θ
JA
Thermal Resistance
θ
JA
8-Lead PDIP Package (N-8) . . . . . . . . . . . . . . . . . 103
°C/W
8-Lead SOIC Package (R-8) . . . . . . . . . . . . . . . . . 158
°C/W
8-Lead TSSOP Package (RU-8) . . . . . . . . . . . . . . 240
°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . 150
°C
Operating Temperature Range . . . . . . . . . . – 40
°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN FUNCTION DESCRIPTIONS
#(
*)
Name Function
1(7)
VREF
DAC Reference Input Pin. Establishes DAC full-
scale voltage. Constant input resistance versus
code.
2 (8) RFB
Internal Matching Feedback Resistor. Connect
to external op amp output.
3 (1) IOUT
DAC Current Output, full-scale output 1 LSB
less than reference input voltage –VREF.
4 (2) GND
Analog and Digital Ground.
5 (3)
LD
Load Strobe, Level-Sensitive Digital Input.
Transfers shift-register data to DAC register
while active low. See truth table for operation.
6 (4) SRI
12-Bit Serial Register Input, data loads directly
into the shift register MSB first. Extra leading
bits are ignored.
7 (5) CLK
Clock Input, positive-edge clocks data into shift
register.
8 (6) VDD
Positive Power Supply Input. Specified range of
operation 5 V
± 10%.
*Note Pin numbers in parenthesis represent the rotated pinout of the
DAC8043A1ES and DAC8043A1FS models.
DAC8043AE/F PIN CONFIGURATIONS
1
4
5
8
SOIC-8
DAC8043A
ES/FS
1
4
5
8
TSSOP-8
DAC8043A
FRU
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
IOUT
GND
LD
RFB
VREF
VDD
CLK
SRI
PDIP-8
DAC8043A
EP/FP
DAC8043A1E AND DAC8043A1F PIN CONFIGURATION
(Rotated Pinout)
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
IOUT
GND
LD
RFB
VREF
VDD
CLK
SRI
SOIC-8
DAC8043A1ES
DAC8043A1FS
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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